[1] 苏明. 高层次综合算法及其系统的研究. 清华大学博士学位论文, 1993. [2] 苏明, 元彦宏, 薛宏熙等. 基于浓度扩散的调度算法. 计算机学报, 1993, 16(4), pp. 257 - 264. [3] 苏明, 薛宏熙, 洪先龙. 强时间约束条件下的调度优化算法. 计算机辅助设计与图形学学报, 1993, 5(1), pp. 13 - 17. [4] 苏明, 薛宏熙, 洪先龙. 数字系统的高层次综合. 计算机辅助设计与图形学学报, 1993, 5(2), pp. 81 - 87. [5] Parker A C, Pizarro J, Mlinar M. MAHA: A Program for Data Path Synthesis. Proc. Of the 23rd DAC, 1986, pp. 461 - 466. [6] Camposano R, Rosenstiel W. Synthesizing Circuits From Behavioral Descriptions. IEEE Trans. On CAD, 1989, 8(2), pp. 171 -180. [7] Paulin P G, Knight J P. Force-Directed Scheduling for the Behavioral Synthesis of ASIC's. IEEE Trans. On CAD, 1989, 8(6), pp. 661 - 679 [8] Devadas S, Newton A R. Algorithms for Hardware Allocation in Data Path Synthesis. IEEE Trans. On CAD, 1989, 8(7), pp. 768 - 781. [9] Lee J H, Hsu Y C, Lin Y L. A New Integer Linear Programming Formulation for the Scheduling Program in Data Path Synthesis. Proc. of ICCAD, 1989, pp.20 - 23. [10] Chen C Y R, Moriez M Z. Data Path Scheduling for Two-Level Pipelining. Proc. of ICCD, 1989, pp.432 - 435. [11] Thomas D E, Lagnese E D. Algorithmic and Register Transfer Level Synthesis: the System Architect's workbench. Norwell, Massachusetts, Kluwer Academic Publishers, 1990. [12] McFarland M C, Parker A C, Camposano R. The High-Level Synthesis of Digital Systems. Proceedings of the IEEE, 1990, 76(2), pp. 301 - 318. [13] Brewer F, Gajski D D. Chippe: A System for Constraint Driven Behavioral Synthesis. IEEE Trans. on CAD, 1990, 9(7), pp. 681 - 694. [14] Micheli G D, Ku D C and Mailhot F et al. The Olympus Synthesis System. IEEE Design and Test. 1990, 7(5), pp. 37 - 53. [15] Dutt N D, Hadley T, Gajski D D. An Intermediate Representation for Behavioral Synthesis. Proc. of the 27th DAC, 1990, pp. 14 - 19. [16] Ku D C and Micheli G D. Relative Scheduling under Timing Constraints. Proc. of the 27th DAC, 1990, pp.59 - 64. [17] Papachristou C A, Konuk H. A linear Program driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm. Proc. of the 27th DAC, 1990, pp.77 - 83. [18] Ly T A, Elwood W L, Girczyc E F. A Generalized Interconnect Model for Data Path Synthesis. Proc. of the 27th DAC, 1990, pp.168 - 173. [19] McNall K N, Casavant A E. Automatic Operator Configuration in the Synthesis of Pipelined Architectures. Proc. of the 27th DAC, 1990, pp.174 - 179. [20] Huang C Y, Chen Y S, Lin Y L et al. Data Path Allocation Based on Bipartite Weighted Matching. Proc. of the 27th DAC, 1990, pp.499 - 504. [21] Jain R. MOSP: Module Selection for Pipelined Designs with Multi-cycle Operations. Proc. of ICCAD, 1990, pp.212 - 215. [22] Nestor J A, Krishnamoorthy G. SALSA: a New Approach to Scheduling with Timing Constraints Proc. of ICCAD, 1990, pp.262 - 265. [23] Grass W. A Branch and Bound Method for Optimal Transformation of Data Flow Graphs for Observing Hardware Constraints. Proc. of EDAC, 1990, pp.73 - 77. [24] Camposano R. Path-Based Scheduling for Synthesis. IEEE Trans. on CAD, 1991, 10(1), pp. 85 - 93. [25] Bergamaschi R A, Camposano R, Payer M. Data Path Synthesis Using Path Analysis. Proc. of the 28th DAC, 1991, pp.591 - 596. [26] Hwang C T, Hsu Y C, Lin Y L. Scheduling for Functional Pipelining and Loop Winding. Proc. of the 28th DAC, 1991, pp.764 - 769. [27] Su M, Xue H X, Hong X L. Diffusion Based Scheduling Algorithm for High Level Synthesis. Proc. of the 2nd CAD / Graphics, 1991, pp.497 - 502. [28] Nourani M, Papachristou C. Move Frame Scheduling and Mixed Scheduling Allocation for the Automated Synthesis of Digital Systems. Proc. of the 29th DAC, 1992, pp.99 - 105. [29] Wakabayashi K, Tanaka H. Global Scheduling Independent of Control Dependencies Based on Condition Vectors. Proc. of the 29th DAC, 1992, pp.112 - 115. [30] Gebotys C H. Optimal Scheduling and Allocation of Embedded VLSI Chips. Proc. of the 29th DAC, 1992, pp.116 - 119 [31] Rim M, Jain R, Leone R D. Optimal Allocation and Binding in High-Level Synthesis. Proc. of the 29th DAC, 1992, pp.120 - 123. [32] Su M, Xue H X, Hong X L. A Global Scheduling Algorithm for CDFG with Nested Conditional Branches. Proc. of the 3rd International CAD / Graphics, 1993, pp.526 - 530. [33] Giovanni De Micheli. Synthesis and Optimization of Digital Circuit. McGraw-Hill Inc..