entity Counter_Element is 　　　　port(Cin, Clk: in Bit; 　　　　　　Cout, Bout: out Bit); 　　end Counter_Element; 　　architecture Pure_Behavior of Counter_Element is 　　　signal DffOut: Bit:= '0'; 　　　signal ExorOut: Bit:= '0'; 　　begin 　　　L1: Bout <= DffOut; 　　　L2: ExorOut <= DffOut xor Cin; 　　　L3: Cout <= DffOut and Cin; 　　　L4: process(Clk) 　　　　begin 　　　　　if Clock = '1' then 　　　　　　　DffOut <= ExorOut; 　　　　　end if; 　　　　end process; 　　end Pure_Behavior;

图2.19 一位计数器

　　设Clk='0', '1' after 1 ns, '0' after 2 ns, '1' after 3 ns, '0' after 4 ns,
　　　　　'1' after 5 ns, '0' after 6 ns, '1' after 7 ns, '0' after 8 ns,
　　　　　'1' after 9 ns, '0' after 10 ns, '1' after 11 ns, '0' after 12 ns, '1' after 13 ns;
　　　Cin='0', '1' after 2 ns, '0' after 4 ns, '1' after 6 ns, '0' after 8 ns,
　　　　　'1' after 10 ns, '0' after 12 ns;