| 例1. Entity PLA is port( In0, In1, In2, In3, In4: in Bit; －－ 输入端口 Out0, Out1, Out3,2, Out3, Out4, Out5, Out6: out Bit); －－ 输出端口 end PLA; Architecture Behavioral of PLA is －－ 以下行为描述 type PLA_Matrix is array ( 0 to 9, 0 to 6) of Bit; constant PLA_Outputs: PLA_Matrix := －－ 类似于查找表 ( －－行列表示PLA的输入值， ('0', '0', '0', '0', '0', '1', '0'), －－ 矩阵中的值表示PLA的输出值。 ('0', '0', '0', '0', '0', '1', '0'), －－ 类似于真值表。 ('0', '1', '1', '0', '0', '1', '0'), ('0', '1', '0', '0', '1', '1', '0'), ('1', '1', '1', '0', '1', '1', '0'), ('1', '1', '0', '1', '0', '0', '0'), ('1', '0', '1', '1', '0', '0', '0'), ('1', '0', '1', '1', '0', '0', '0'), ('1', '0', '0', '1', '0', '0', '1'), ('0', '0', '1', '1', '0', '0', '1') ); begin process variable New_State: Integer; begin if In0 = '0' and In3='0' and In4='0' then New_State := 0; elsif In1 = '0' and In3='0' and In4='0' then New_State := 1; elsif In0 = '1' and In1='1' and In3='0' and In4='0' then New_State := 2; elsif In2 = '0' and In3='0' and In4='1' then New_State := 3; elsif In2 = '1' and In3='0' and In4='1' then New_State := 4; elsif In0 = '1' and In1='0' and In3='1' and In4='1' then New_State := 5; elsif In0 = '0' and In1='0' and In3='1' and In4='1' then New_State := 6; elsif In1 = '1' and In3='1' and In4='1' then New_State := 7; elsif In2 = '0' and In3='1' and In4='0' then New_State := 8; elsif In2 = '1' and In3='1' and In4='1' then New_State := 9; end if; －－根据输入值的组合，确定新状态。 Out0 <= PLA_Outputs(New_State, 0); Out1 <= PLA_Outputs(New_State, 1); Out2 <= PLA_Outputs(New_State, 2); Out3 <= PLA_Outputs(New_State, 3); Out4 <= PLA_Outputs(New_State, 4); Out5 <= PLA_Outputs(New_State, 5); Out6 <= PLA_Outputs(New_State, 6); wait on In0, In1, In2, In3, In4; end process; end Behavioral; 上面的行为描述是对表2.6所示的的真值表的描述。
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