|
节拍
|
指令
|
编码
|
/MIO
|
REQ
|
/WE
|
A
|
B
|
SCI
|
SSH
|
I8-6
|
I5-3
|
I2-0
|
SST
|
DC1
|
DC2
|
操作功能说明
|
|
1100
|
1
|
*
|
*
|
0101
|
0101
|
01
|
00
|
011
|
001
|
001
|
000
|
000
|
0111
|
0->R5(PCH),DI#=0 | ||
|
1000
|
1
|
*
|
*
|
0100
|
0100
|
01
|
00
|
011
|
001
|
001
|
000
|
000
|
0000
|
0->R4(PCL) | ||
|
0000
|
1
|
*
|
*
|
0100
|
0100
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R4->ARL;R4+1->R4,C0 | ||
|
0010
|
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
1011
|
R5->ARH;R5+C0->R5 | ||
|
0110
|
0
|
0
|
1
|
*
|
*
|
*
|
*
|
001
|
*
|
*
|
*
|
000
|
0001
|
MEM->IR; | ||
|
0100
|
ADD | 0000 DRSR |
1
|
*
|
*
|
00SR
|
00DR
|
00
|
00
|
011
|
000
|
001
|
001
|
000
|
0000
|
DR+SR->DR;CVSZ |
| SUB | 0001 DRSR |
1
|
*
|
*
|
00SR
|
00DR
|
01
|
00
|
011
|
001
|
001
|
001
|
000
|
0000
|
DR-SR->DR;CVSZ | |
| AND | 0010 DRSR |
1
|
*
|
*
|
00SR
|
00DR
|
00
|
00
|
011
|
100
|
001
|
001
|
000
|
0000
|
DR∧SR->DR;CVSZ | |
| CMP | 0011 DRSR |
1
|
*
|
*
|
00SR
|
00DR
|
01
|
00
|
001
|
001
|
001
|
001
|
000
|
0000
|
DR-SR;CVSZ | |
| MOV | 0100 DRSR |
1
|
*
|
*
|
00SR
|
00DR
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
SR->DR | |
| DEC | 1001 00DR |
1
|
*
|
*
|
*
|
00DR
|
00
|
00
|
011
|
001
|
011
|
001
|
000
|
0000
|
DR-1->DR | |
| SHR | 1010 00DR |
1
|
*
|
*
|
*
|
00DR
|
00
|
00
|
101
|
000
|
011
|
101
|
000
|
0000
|
DR/2->DR;C | |
| SHL | 1010 01DR |
1
|
*
|
*
|
*
|
00DR
|
00
|
00
|
111
|
000
|
011
|
110
|
000
|
0000
|
DR*2->DR;C | |
| INC | 1100 DR |
1
|
*
|
*
|
*
|
DR
|
01
|
00
|
011
|
000
|
011
|
001
|
000
|
0000
|
DR+1->DR(/4-7) | |
| IN | 1010 10IO |
0
|
1
|
1
|
*
|
0000
|
00
|
00
|
011
|
000
|
111
|
000
|
000
|
0000
|
(PORT)->R0 | |
| OUT | 1010 11IO |
0
|
1
|
0
|
*
|
0000
|
00
|
00
|
001
|
000
|
011
|
000
|
001
|
0000
|
R0->(PORT) | |
| CLC | 1111 1000 |
1
|
*
|
*
|
*
|
*
|
*
|
*
|
001
|
*
|
*
|
011
|
000
|
0000
|
C:=0 | |
| STC | 1111 1001 |
1
|
*
|
*
|
*
|
*
|
*
|
*
|
001
|
*
|
*
|
100
|
000
|
0000
|
C:=1 | |
|
0111
|
STO | 1011 10SR |
1
|
*
|
*
|
*
|
1000
|
00
|
00
|
001
|
000
|
011
|
000
|
000
|
0010
|
R8->ARL |
| LOD | 1011 11DR |
1
|
*
|
*
|
*
|
1000
|
00
|
00
|
001
|
000
|
011
|
000
|
000
|
0010
|
R8->ARL | |
| PUSH | 1011 00SR |
1
|
*
|
*
|
*
|
0110
|
00
|
00
|
011
|
001
|
011
|
000
|
000
|
0010
|
R6-1->R6,ARL,C0 | |
| POP | 1011 01DR |
1
|
*
|
*
|
0110
|
0110
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R6->ARL;R6+1->R6,C0 | |
| PUSHF | 1111 1010 |
1
|
*
|
*
|
*
|
0110
|
00
|
00
|
011
|
001
|
011
|
000
|
000
|
0010
|
R6-1->R6,ARL,C0 | |
| POPF | 1111 1011 |
1
|
*
|
*
|
0110
|
0110
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R6->ARL;R6+1->R6,C0 | |
| MVD | 1101 DR DATA |
1
|
*
|
*
|
0100
|
0100
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R4->ARL;R4+1->R4,C0 | |
| JR | 1110 11**OFFSET |
1
|
*
|
*
|
0100
|
0100
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R4->ARL;R4+1->R4,C0 | |
| JNZ | 1110 1001OFFSET |
1
|
*
|
*
|
0100
|
0100
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R4->ARL;R4+1->R4,C0 | |
| JZ | 1110 1000OFFSET |
1
|
*
|
*
|
0100
|
0100
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R4->ARL;R4+1->R4,C0 | |
| JNC | 1110 1011OFFSET |
1
|
*
|
*
|
0100
|
0100
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R4->ARL;R4+1->R4,C0 | |
| JC | 1110 1010OFFSET |
1
|
*
|
*
|
0100
|
0100
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R4->ARL;R4+1->R4,C0 | |
| CALL | 1111 1100 |
1
|
*
|
*
|
*
|
0110
|
00
|
00
|
011
|
001
|
011
|
000
|
000
|
0010
|
R6(SP)-1->R6,ARL,C0 | |
| RET | 1111 1101 |
1
|
*
|
*
|
0110
|
0110
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R6->ARL;R6+1->R6,C0 | |
|
0011
|
STO | 1011 10SR |
1
|
*
|
*
|
*
|
1001
|
00
|
00
|
001
|
000
|
011
|
000
|
000
|
0011
|
R9->ARH |
| LOD | 1011 11DR |
1
|
*
|
*
|
*
|
1001
|
00
|
00
|
001
|
000
|
011
|
000
|
000
|
0011
|
R9->ARH | |
| PUSH | 1011 00SR |
1
|
*
|
*
|
*
|
0111
|
11
|
00
|
011
|
001
|
011
|
000
|
000
|
0011
|
R7-C0->R7,ARH | |
| POP | 1011 01DR |
1
|
*
|
*
|
0111
|
0111
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
0011
|
R7->ARH;R7+C0->R7 | |
| PUSHF | 1111 1010 |
1
|
*
|
*
|
*
|
0111
|
11
|
00
|
011
|
001
|
011
|
000
|
000
|
0011
|
R7-C0->R7,ARH | |
| POPF | 1111 1011 |
1
|
*
|
*
|
0111
|
0111
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
0011
|
R7->ARH;R7+C0->R7 | |
| MVD | 1101 DRDATA |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
0011
|
R5->ARH;R5+C0->R5 | |
| JR | 1110 11**OFFSET |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
0011
|
R5->ARH;R5+C0->R5 | |
| JNZ | 1110 1001OFFSET |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
0011
|
R5->ARH;R5+C0->R5 | |
| JZ | 1110 1000OFFSET |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
0011
|
R5->ARH;R5+C0->R5 | |
| JNC | 1110 1011OFFSET |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
0011
|
R5->ARH;R5+C0->R5 | |
| JC | 1110 1010OFFSET |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
0011
|
R5->ARH;R5+C0->R5 | |
| CALL | 1111 1100 |
1
|
*
|
*
|
*
|
0111
|
11
|
00
|
011
|
001
|
011
|
000
|
000
|
0011
|
R7(SP)-C0->R7,ARH | |
| RET | 1111 1101 |
1
|
*
|
*
|
0111
|
0111
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
0011
|
R7->ARH;R7+C0->R7 | |
|
0001
|
STO | 1011 10SR |
0
|
0
|
0
|
*
|
00SR
|
00
|
00
|
001
|
000
|
011
|
000
|
001
|
0000
|
SR->MEM |
| LOD | 1011 11DR |
0
|
0
|
1
|
*
|
00DR
|
00
|
00
|
011
|
000
|
111
|
000
|
000
|
0000
|
MEM->DR | |
| PUSH | 1011 00SR |
0
|
0
|
0
|
*
|
00SR
|
00
|
00
|
001
|
000
|
011
|
000
|
001
|
0000
|
SR->MEM | |
| POP | 1011 01DR |
0
|
0
|
1
|
*
|
00DR
|
00
|
00
|
011
|
000
|
111
|
000
|
000
|
0000
|
MEM->DR | |
| PUSHF | 1111 1010 |
0
|
0
|
0
|
*
|
*
|
*
|
*
|
001
|
*
|
*
|
*
|
011
|
0000
|
FLAG->MEM | |
| POPF | 1111 1011 |
0
|
0
|
1
|
*
|
*
|
*
|
*
|
001
|
*
|
*
|
010
|
000
|
0000
|
MEM->FLAG | |
| MVD | 1101 DRDATA |
0
|
0
|
1
|
*
|
DR
|
00
|
00
|
011
|
000
|
111
|
000
|
000
|
0000
|
DATA->DR | |
| JR | 1110 11**OFFSET |
0
|
0
|
1
|
0100
|
0100
|
00
|
00
|
011
|
000
|
101
|
000
|
000
|
0000
|
R4+OFFSET->R4,C0 | |
| JNZ | 1110 1001OFFSET |
0
|
0
|
1
|
0100
|
0100
|
00
|
00
|
0/Z1
|
000
|
101
|
000
|
000
|
0000
|
(R4+OFFSET->R4,C0)*/Z | |
| JZ | 1110 1000OFFSET |
0
|
0
|
1
|
0100
|
0100
|
00
|
00
|
0Z1
|
000
|
101
|
000
|
000
|
0000
|
(R4+OFFSET->R4,C0)*Z | |
| JNC | 1110 1011OFFSET |
0
|
0
|
1
|
0100
|
0100
|
00
|
00
|
0/C1
|
000
|
101
|
000
|
000
|
0000
|
(R4+OFFSET->R4,C0)*/C | |
| JC | 1110 1010OFFSET |
0
|
0
|
1
|
0100
|
0100
|
00
|
00
|
0C1
|
000
|
101
|
000
|
000
|
0000
|
(R4+OFFSET->R4,C0)*C | |
| CALL | 1111 1100 |
0
|
0
|
0
|
*
|
0101
|
00
|
00
|
001
|
000
|
011
|
000
|
001
|
0000
|
R5->MEM | |
| RET | 1111 1101 |
0
|
0
|
1
|
*
|
0100
|
00
|
00
|
011
|
000
|
111
|
000
|
000
|
0000
|
MEM->R4 | |
|
0100
|
JR | 1110 11**OFFSET |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
011
|
000
|
101
|
000
|
100
|
0000
|
R5+D+C0->R5 |
| JNZ | 1110 1001OFFSET |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
0/Z1
|
000
|
101
|
000
|
100
|
0000
|
(R5+D+C0->R5)*/Z | |
| JZ | 1110 1000OFFSET |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
0Z1
|
000
|
101
|
000
|
100
|
0000
|
(R5+D+C0->R5)*Z | |
| JNC | 1110 1011OFFSET |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
0/C1
|
000
|
101
|
000
|
100
|
0000
|
(R5+D+C0->R5)*/C | |
| JC | 1110 1010OFFSET |
1
|
*
|
*
|
0101
|
0101
|
11
|
00
|
0C1
|
000
|
101
|
000
|
100
|
0000
|
(R5+D+C0->R5)*C | |
|
1111
|
CALL | 1111 1100 |
1
|
*
|
*
|
*
|
0110
|
00
|
00
|
011
|
001
|
011
|
000
|
000
|
0010
|
R6(SP)-1->R6,ARL,C0 |
| RET | 1111 1101 |
1
|
*
|
*
|
0110
|
0110
|
01
|
00
|
010
|
000
|
011
|
000
|
000
|
0010
|
R6->ARL;R6+1->R6,C0 | |
|
1011
|
CALL | 1111 1100 |
1
|
*
|
*
|
*
|
0111
|
11
|
00
|
011
|
001
|
011
|
000
|
000
|
0011
|
R7(SP)-C0->R7,ARH |
| RET | 1111 1101 |
1
|
*
|
*
|
0111
|
0111
|
11
|
00
|
010
|
000
|
011
|
000
|
000
|
0011
|
R7->ARH;R7+C0->R7 | |
|
1001
|
CALL | 1111 1100 |
0
|
0
|
0
|
*
|
0100
|
00
|
00
|
001
|
000
|
011
|
000
|
001
|
0000
|
R4->MEM |
| RET | 1111 1101 |
0
|
0
|
1
|
*
|
0101
|
00
|
00
|
011
|
000
|
111
|
000
|
000
|
0000
|
MEM->R5 | |
|
0101
|
CALL | 1111 1100 |
1
|
*
|
*
|
1011
|
0101
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
R11->R5 |
| JMP | 1111 1111 |
1
|
*
|
*
|
1011
|
0101
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
R11->R5 | |
| TPC | 1100 0100 |
1
|
*
|
*
|
1101
|
0101
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
R13->PC(R5) | |
| FPC | 1100 0101 |
1
|
*
|
*
|
0101
|
1101
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
PC(R5)->R13 | |
| TSP | 1100 0110 |
1
|
*
|
*
|
1111
|
0111
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
R15->SP(R7) | |
| FSP | 1100 0111 |
1
|
*
|
*
|
0111
|
1111
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
SP(R7)->R15 | |
|
0100
|
CALL | 1111 1100 |
1
|
*
|
*
|
1010
|
0100
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
R10->R4 |
| JMP | 1111 1111 |
1
|
*
|
*
|
1010
|
0100
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
R10->R4 | |
| TPC | 1100 0100 |
1
|
*
|
*
|
1100
|
0100
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
R12->PC(R4) | |
| FPC | 1100 0101 |
1
|
*
|
*
|
0100
|
1100
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
PC(R4)->R12 | |
| TSP | 1100 0110 |
1
|
*
|
*
|
1110
|
0110
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
R14->SP(R6) | |
| FSP | 1100 0111 |
1
|
*
|
*
|
0110
|
1110
|
00
|
00
|
011
|
000
|
100
|
000
|
000
|
0000
|
SP(R6)->R14 |